diff --git a/Diplomschrift.bib b/Diplomschrift.bib
index 28683e8..d12a391 100644
--- a/Diplomschrift.bib
+++ b/Diplomschrift.bib
@@ -91,6 +91,15 @@
     urldate = {2020-03-29},
 }
 
+@inbook{vhdl-types,
+    author    = {Klaus Fricke},
+    title     = {Digitaltechnik - Lehr- und Übungsbuch für Elektrotechniker und Informatiker},
+    publisher = {Springer Vieweg},
+    year      = {2013},
+    doi       = {10.1007/978-3-8348-2213-0},
+    chapter   = {15.3},
+}
+
 @online{riscv-compliance,
     author = {Jeremy Bennett, Lee Moore},
     title  = {RISC-V Compliance Task Group},
diff --git a/sections/soc/soc.tex b/sections/soc/soc.tex
index 6a20546..22d06fc 100644
--- a/sections/soc/soc.tex
+++ b/sections/soc/soc.tex
@@ -54,7 +54,7 @@ While the Digilent board offers fewer IO options, the DDR3 memory can be interfa
 
 \section{FPGA Tooling}
 
-FPGA design is done using a Hardware Description Language (HDL). The two most well-known HDLs are Verilog and VHDL (VHSIC (Very high speed integrated circuit) HDL). As part of our studies at HTL, we exclusively worked with VHDL. For this reason, and because VHDL offers a better type system, it was chosen as the language of choice for the project.
+FPGA design is done using a Hardware Description Language (HDL). The two most well-known HDLs are Verilog and VHDL (VHSIC (Very high speed integrated circuit) HDL). As part of our studies at HTL, we exclusively worked with VHDL. For this reason, and because VHDL offers a strong type system~\cite{vhdl-types}, it was selected as the language of choice for the project.
 
 \subsection{Vendor Tools}