diff --git a/charts/flowchart_textadv.pdf b/charts/flowchart_textadv.pdf new file mode 100644 index 0000000..656ec04 Binary files /dev/null and b/charts/flowchart_textadv.pdf differ diff --git a/charts/flowchart_textadv.svg b/charts/flowchart_textadv.svg new file mode 100644 index 0000000..fc3cfb2 --- /dev/null +++ b/charts/flowchart_textadv.svg @@ -0,0 +1,447 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/main.pdf b/main.pdf index bfbfdd6..b524802 100644 --- a/main.pdf +++ b/main.pdf @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7e314eadc8881810bedba297f6825aad35312b0422b745cb526c4eb43dac256d -size 3593935 +oid sha256:9cf253f620c4c4b1800e21b58f30642be9b19bdbdbfa23c790adf81a25c4654d +size 3556721 diff --git a/main.tex b/main.tex index bed9adc..ac8f20a 100644 --- a/main.tex +++ b/main.tex @@ -186,13 +186,10 @@ geschlechtsunabh"angig verstanden werden soll. \section{Projektmanagement} \subsection{Schlussfolgerung / Projekterfahrung} \input{sections/Anhang/schlussfolgerung.tex} -\subsection{Projektplanung} -\DP\input{sections/Anhang/planung.tex} \subsection{Projektterminplanung} \allAuth\input{sections/Anhang/Projektterminplanung/projektterminplanung.tex} -%\subsection{Arbeitsnachweis Diplomarbeit} -%\MR\input{sections/Anhang/Arbeitsnachweis/arbeitsnachweisMR.tex} +\allAuth\input{sections/Anhang/flash.tex} \AB\subfile{sections/vhdl_intro/vhdl_intro.tex} \end{appendices} diff --git a/planung/DP/aufgabenstellung.tex b/planung/DP/aufgabenstellung.tex index 6e45a87..4f790c3 100644 --- a/planung/DP/aufgabenstellung.tex +++ b/planung/DP/aufgabenstellung.tex @@ -5,16 +5,14 @@ about the internal workings of a computer system and the lack of material to demonstrate these, hardware should be developed for educational purposes. This hardware should not be too complex to understand but still demonstrate basic tasks of a computer system. The targeted computing tasks are human interface -device controllers, under which a \textbf{D}igital to \textbf{A}nalog -\textbf{C}onverter\footnote{From now on reffered to simply as DAC} and a serial -console with TIA-/EIA-232 compliant voltage levels were chosen. For these -peripherials schematics and a working implementation in the hardware building -style of the hackerspace should be built. All nescessary hardware will be -provided by the Hackerspace. If possible already present hardware should be -used, if impossible new one will be ordered. All schematics should, where +device controllers, for which +schematics and a working implementation in the hardware building +style of the Hackerspace should be built. All nescessary hardware will be +provided by the Hackerspace. If possible, already present hardware should be +used, or, if impossible, new one will be ordered. All schematics should, where possible, be constructed in Free software such as Kicad or GNU-EDA. -If possible software-examples should be written as well, though the complexity -of these are coupled to the time left to spend on the project. Software should +If possible, software-examples should be written as well, though the complexity +of these is coupled to the time left to spend on the project. Software should be written in C, the coding convention is left to the implementer. diff --git a/sections/Anhang/Projektterminplanung/projektterminplanung.tex b/sections/Anhang/Projektterminplanung/projektterminplanung.tex index 3c05ff9..e298a6f 100644 --- a/sections/Anhang/Projektterminplanung/projektterminplanung.tex +++ b/sections/Anhang/Projektterminplanung/projektterminplanung.tex @@ -247,10 +247,11 @@ Table \ref{tab:brauns_work} shows the times worked. \hline \hline 2020-04-01 & \textbf{SUM} & 277h\\ + \hline \caption{Work time reference - Brauns} \label{tab:brauns_work} \end{longtable} - +\newpage \paragraph{Plank} Table \ref{tab:plank_work} shows the times worked. diff --git a/sections/Anhang/flash.tex b/sections/Anhang/flash.tex new file mode 100644 index 0000000..d97459f --- /dev/null +++ b/sections/Anhang/flash.tex @@ -0,0 +1,57 @@ +\section{Contents of the flash drive} + +This section outlines the contents of the flash drive, which are two folders +``AB`` and ``DP``, one containg the files of Armin Brauns and one for Daniel +Plank respectively. + +\subsection{Armin Brauns} + +\begin{itemize} +\item \texttt{external/}: External dependencies as submodules +\item \texttt{firmware/}: See \texttt{firmare/README.md} +\item \texttt{sim/}: GHDL wave options and GTKWave save files for test bench + traces +\item \texttt{tests/}: High-level tests + \begin{itemize} + \item \texttt{formal/}: SymbiYosys formal verification tests + \item \texttt{riscv-compliance-target/}: YARM target for RISC-V compliance + test suite + \end{itemize} +\item \texttt{vhdl/}: All VHDL code + \begin{itemize} + \item \texttt{components/}: Various SoC components + \item \texttt{core/}: The YARM processor core + \item \texttt{memories/}: Various memory primitives, tweaked to work with + yosys + \item \texttt{simulation/}: Simulation models for primitives and external + IP + \item \texttt{tests/}: Test benches + \end{itemize} +\end{itemize} + +\subsection{Daniel Plank} + +\begin{table}[H] + \centering + \begin{tabular}{| c | r |} + \hline + \textbf{Directory} & \textbf{Contents}\\ + \hline + \hline + code & Code sampkes written for this thesis\\ + \hline + dipl & The source code for this thesis in \LaTeX\\ + \hline + documents & Datasheets and documents referenced in this thesis\\ + \hline + MS1 & The original milestone test plans, high level design and documents for MS1\\ + \hline + schematics & Schematics for KiCAD used in this thesis\\ + \hline + textadv & The textadventure written for the hardware peripherials\\ + \hline + \end{tabular} + \caption{Contents of the DP directory on the flash drive} + \label{tab:flash_DP} +\end{table} + diff --git a/sections/Anhang/schlussfolgerung.tex b/sections/Anhang/schlussfolgerung.tex index b92559d..d77c119 100644 --- a/sections/Anhang/schlussfolgerung.tex +++ b/sections/Anhang/schlussfolgerung.tex @@ -1,8 +1,8 @@ -Aus der Projektimplementierung konnten viele Lehren gezogen werden. Messungen -welche mittels des Analog Discovery durchgeführt wurden sind bis zu ungefähr -1MHz Frequenz gut zu gebrauchen werden danach jedoch sehr stark fehlerhaft. Alle +Aus der Projektimplementierung konnten viele Lehren gezogen werden. Messungen, +welche mittels des Analog Discoverys durchgeführt wurden, sind bis zu ungefähr +1MHz Frequenz gut zu gebrauchen, werden danach jedoch sehr stark fehlerhaft. Alle Bauteile in THT Bauform zu verwenden vereinfachte Messungen am Steckbrett erheblich, jedoch werden diese bei hohen Frequenzen unzuverlässig. Viele -Implementationsdetails wurden durch mündlich übergebene Hinweise verbessert -was zeigt wie wichtig zwischenmenschliche Kommunikation in technischen Bereichen -ist. +Implementationsdetails wurden durch mündlich übergebene Hinweise verbessert, +was zeigt, wie wichtig zwischenmenschliche Kommunikation in technischen +Bereichen ist. diff --git a/sections/DP/plan.tex b/sections/DP/plan.tex index 14961ff..1bcd931 100644 --- a/sections/DP/plan.tex +++ b/sections/DP/plan.tex @@ -4,21 +4,22 @@ Planning of the peripherals was done based on the information provided on large parts by David Oberhollenzer. A lot of his advice contributed heavily to the direction the development went. -\subsubsection{Peripherial selection} +\subsubsection{Peripheral selection} The selection of the hardware peripherals was done based on implementation difficulty, common use in computer systems, relevance in current times and -wether they were fitting for demonstrative purposes. +whether they were fitting for demonstrative purposes. -\paragraph{Serial communication interface} +\paragraph{Serial Communication interface} Serial communication interfaces have been around for a long time. They have been used for many different applications from early mouse pointer devices \cite{232mouse} to user input terminals\cite{vt100} which are far away from the real computer system. They are still very common in -smaller embedded sytems and in the server space where they are used as a simple +smaller embedded systems and in the server space, where they are used as a +simple and less error prone way to interface with the operating system and programs -running there. They are fairly easy to implement as there are a interface +running there. They are fairly easy to implement as there are interface ICs which provide a more generic interface for serial communications \cite{pc16550}. Most SOCs \footnote{SOC... System on a Chip} have some form of serial communication @@ -33,24 +34,24 @@ parallel-ports for expansions and the ISA-Bus \footnote{ISA...Industry Standard Architecture} was for some time the main way of expansion for PCs \footnote{PC in this thesis referrs to Computer Systems using the x86 -Architecture}. Most younger people remeber parallel ports as the port for -printers on their home PCs. A prallel port is easy to implement because it has -simmilar use of control, data and address lines like a processor uses internally -anyways\cite{laval_parallel}. Usage of the standard IEEE 1284 port limits the +Architecture}. Most younger people remember parallel ports as the port for +printers on their home PCs. A parallel port is easy to implement because it has +simmilar use of control, data and address lines as a processor uses internally +anyway\cite{laval_parallel}. Usage of the standard IEEE 1284 port limits the design to the signals on this port or makes the use of the signals on this port obligatory. \paragraph{Digital to Analog Converter} -Digital to Analog Converters or more commonly DACs are used on all modern PCs +Digital to Analog Converters (or more commonly DACs) are used on all modern PCs for sound output. They have been around for longer and some external sound card -interfaces have been standardisedlike AC '97\cite{ac97}. Implementation of a +interfaces have been standardised like AC '97\cite{ac97}. Implementation of a standard audio interface requires higher speed connections or more precise timing for ac97 for example. Earlier computer systems did not have a sound card -as it doesn't have import usage for computing and user input tasks and later +as it doesn't have important usage for computing and user input tasks and later on computer systems only had a PC speaker for diagnostics such as the IBM PC AT \cite{ibmpc} which can only procude one specific frequency and does not have a -DAC. A dac is not easy to implement as it requires a constant sampling rate and +DAC. A DAC is not easy to implement as it requires a constant sampling rate and a buffer to be of any practical use. \paragraph{Graphical output / GPU} @@ -61,10 +62,10 @@ either a heavy load on the processor or dedicated hardware and due to the mostly scientific use it was easier to just print the caracters as letters via a printer. Drawing characters onto a screen is by itself not an easy task as it requires, for example for -VGA a Digital to Analog Converter with 25MHz sampling rate and a buffer to +VGA, a Digital to Analog Converter with 25MHz sampling rate and a buffer to contain all needed data for one frame or at least parts of it, while the CPU -renders the frame\cite{vga}. Screen output is one of the if not the most common -form of output on a computer today. +renders the frame\cite{vga}. Screen output is one of the, if not the most, +common form of output on a computer today. \paragraph{Inter Integrated Circuit} @@ -80,7 +81,7 @@ understanding of IIC as it is only known in technical fields. \paragraph{Utility analysis} Among the above mentioned processor peripherals from the criteria mentioned -before a utility analysis was performed. To do this different point have been +before a utility analysis was performed. To do this, different points have been credited for the criteria mentioned which can be seen in Table \ref{tab:utility_base}. The multipliers in Table \ref{tab:utility_base} have been applied to the points and the sums in Table \ref{tab:utility_result} diff --git a/sections/DP/textadv/main.tex b/sections/DP/textadv/main.tex index 9d5248c..94e784c 100644 --- a/sections/DP/textadv/main.tex +++ b/sections/DP/textadv/main.tex @@ -81,7 +81,7 @@ in figure \ref{fig:textadv_pexfl}. \begin{figure}[H] \centering - \input{charts/flowchart_textadv.tex} + \includesvg[height=.95\textheight]{charts/flowchart_textadv.svg} \caption{A Flow-Chart of the program execution path} \label{fig:textadv_pexfl} \end{figure} diff --git a/sections/abstract.tex b/sections/abstract.tex index 812adaa..56ae2b8 100644 --- a/sections/abstract.tex +++ b/sections/abstract.tex @@ -1,10 +1,9 @@ \begin{otherlanguage}{ngerman} Diese Diplomarbeit beschäftigt sich mit der Arbeitsweise von Prozessoren -und Prozessorperipherie in moderner und traditioneller Form. Sie versucht -anschaulich den +und Prozessorperipherie in moderner und traditioneller Form. Sie versucht den Aufbau eines Computersystems in Hard- und Software zu veranschaulichen -sowie diesen zu erklären. Dafür wurde auf einem XILINX FPGA ein RISC-V32I +sowie diesen zu erklären. Dafür wurde auf einem Xilinx-FPGA ein RISC-V32I Prozessor in VHDL implementiert, sowie diverse Parallelbus-gebundene Hardwareperipherie entwickelt und gebaut. Als Harwareperipherie wurde ein 8-Bit 2-Kanal DAC und eine serielle diff --git a/sections/core/core.tex b/sections/core/core.tex index 610d3d2..50b3cb4 100644 --- a/sections/core/core.tex +++ b/sections/core/core.tex @@ -1,4 +1,4 @@ -\documentclass[../../Diplomschrift.tex]{subfiles} +\documentclass[../../main.tex]{subfiles} \begin{document} @@ -12,7 +12,7 @@ The core implements the \instrset{} architecture as specified by the RISC-V stan \label{fig:core-diagram} \end{figure} -As can be seen in \ref{fig:core-diagram}, it is constructed according to the traditional stages of a RISC pipeline: +As can be seen in \autoref{fig:core-diagram}, it is constructed according to the traditional stages of a RISC pipeline: \begin{description} \item[Fetch] fetches the next instruction from memory. diff --git a/sections/fpga-development.tex b/sections/fpga-development.tex index 2e518ea..3b83dfc 100644 --- a/sections/fpga-development.tex +++ b/sections/fpga-development.tex @@ -1,4 +1,4 @@ -\documentclass[../../Diplomschrift.tex]{subfiles} +\documentclass[../../main.tex]{subfiles} \begin{document} \section{FPGA Development} @@ -60,7 +60,7 @@ To refresh the reader's memory on the VHDL language, and as a quick guide for th \subsubsection{Vendor Tools} -The conventional way to work with FPGA designs is to use the FPGA vendor's development solution for simulation, synthesis and place-and-route. All of these tools are proprietary software specialized to a certain FPGA manufacturer, so a change of hardware also requires changing to a completely different software solution. +The conventional way to work with FPGA designs is to use the FPGA vendor's development environment for simulation, synthesis and place-and-route. All of these tools are proprietary software specialized to a certain FPGA manufacturer, so a change of hardware also requires changing to a completely different software solution. Vendor tools are usually free-of-charge for basic usage, but this also means there is no guaranteed support. During the development of this project, several bugs and missing features were found in vendor tools that required workarounds. diff --git a/sections/intro.tex b/sections/intro.tex index 32342d9..14d8124 100644 --- a/sections/intro.tex +++ b/sections/intro.tex @@ -1,8 +1,8 @@ In early 2018, more than a year before the official start of the project, after searching for a subject for the diploma thesis, the idea of building a computer -from scratch had come up. Multiple suggestions on how to implement it and the -scope of the project were gathered. Originally, the goal was to -design a computer consisting of seperate plug-in cards, one instruction would +from scratch had come up. Multiple suggestions on how to implement it were +gathered. Originally, the goal was to +design a computer consisting of seperate plug-in cards, one instruction residing on each. This would open up the ``black box`` of modern processor design, showing the basic components at a macroscopic scale. @@ -10,8 +10,8 @@ The project's aim was later redirected due to concerns about difficulty, and an FPGA-based design was opted for instead. After several months of implementation time, the project was split into two parts: the -peripherals and the core processor. During the development process, and to get -back to the original goal of making a processor understandable, the +peripherals and the processor core. During the development process, and to get +back to the original goal of making a processor more understandable, the peripherals changed from being implemented in VHDL back to hardware. This increased the required effort, but would result in a far more understandable final product. @@ -25,7 +25,8 @@ software instead. \label{sec:free-software} For most of today's processors, documentation only exists on the execution of -programs (the runtime), not for their internals. In order the have the biggest +programs (the runtime environment), not for their internals. In order to have +the biggest possible educational potential, this project is entirely "Free as in speech": All involved software and hardware designs, as well as all the tools and utilities required to create them, comply with the Free Software Foundation's diff --git a/sections/result.tex b/sections/result.tex index 32ca08e..415dde8 100644 --- a/sections/result.tex +++ b/sections/result.tex @@ -1,4 +1,4 @@ -The project is fully implemented with all functionality originally targeted. +The project has been fully implemented with all functionality originally targeted. The system has been tested and verified. All example code has been documented and tested. Hardware implementations were created using Free software\footnote{See \autoref{sec:free-software}} programs, while the