From 40bc2327fdc5a76c4033f6c5f5d36cdd77566535 Mon Sep 17 00:00:00 2001
From: Xiretza <xiretza@xiretza.xyz>
Date: Sun, 29 Mar 2020 18:05:05 +0200
Subject: [PATCH] Add information about DRAM interface

---
 Diplomschrift.bib    | 6 ++++++
 sections/soc/soc.tex | 4 +++-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/Diplomschrift.bib b/Diplomschrift.bib
index d5cc914..3746535 100644
--- a/Diplomschrift.bib
+++ b/Diplomschrift.bib
@@ -60,6 +60,12 @@
     url    = {https://github.com/enjoy-digital/liteeth}
 }
 
+@software{litedram,
+    author = {Florent Kermarrec},
+    title  = {LiteDRAM},
+    url    = {https://github.com/enjoy-digital/litedram}
+}
+
 @software{open-fpga-loader,
 	author = {Gwenhael Goavec-Merou},
 	title  = {openFPGALoader},
diff --git a/sections/soc/soc.tex b/sections/soc/soc.tex
index 9d58c79..c8d8505 100644
--- a/sections/soc/soc.tex
+++ b/sections/soc/soc.tex
@@ -155,7 +155,9 @@ The exact timing differs between models, so all periods can be customized using
 
 \subsection{DRAM}
 
-% TODO
+The Arty A7 development board contains a 256MB DDR3 memory module. Since the FPGA only contains about 1.8MB of block RAM, of which some is already reserved for various hardware functions (e.g. the text buffer and WS2812 driver), the external memory is absolutely necessary to run larger programs.
+
+Interfacing with DDR3 memory is notoriously difficult, requiring complex logic on both physical and logical layers. For this reason, the Free Software LiteDRAM core~\cite{litedram} is used to integrate the entire memory interface into the SoC. While irrelevant to the SoC, it can still be considered a slight oddity the LiteDRAM core actually contains an entire separate RISC-V core to coordinate initialization of the memory.
 
 \subsection{External Bus}