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Fix work reference

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Xiretza 2020-03-31 23:36:16 +02:00
parent e0cdacd1da
commit 24c636e82a
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GPG Key ID: E51A6C6A1EB378ED
1 changed files with 29 additions and 29 deletions
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58
sections/Anhang/Projektterminplanung/projektterminplanung.tex
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@ -189,64 +189,64 @@ Table \ref{tab:brauns_work} shows the times worked.
\hline
2019-12-01 & 3 & Investigate Free toolchains \\
\hline
2019-01-02 & 0.5 & Code cleanup \\
2020-01-02 & 0.5 & Code cleanup \\
\hline
2019-01-12 & 4 & Work toward free toolchain \\
2020-01-12 & 4 & Work toward free toolchain \\
\hline
2019-01-18 & 5 & Toolchain testing and debugging \\
2020-01-18 & 5 & Toolchain testing and debugging \\
\hline
2019-01-23 & 1 & UART improvements \\
2020-01-23 & 1 & UART improvements \\
\hline
2019-01-24 & 6 & Switch whole project to Free toolchain \\
2020-01-24 & 6 & Switch whole project to Free toolchain \\
\hline
2019-01-25 & 3 & Memory self-test routines \\
2020-01-25 & 3 & Memory self-test routines \\
\hline
2019-01-25 & 0.5 & Prepare ALU for mul/div \\
2020-01-25 & 0.5 & Prepare ALU for mul/div \\
\hline
2019-02-01 & 7 & Simplify core \\
2020-02-01 & 7 & Simplify core \\
\hline
2019-02-02 & 5 & Compliance tests and core bug fixing \\
2020-02-02 & 5 & Compliance tests and core bug fixing \\
\hline
2019-02-02 & 2 & GitLab CI \\
2020-02-02 & 2 & GitLab CI \\
\hline
2019-02-04 & 1 & Update toolchain \\
2020-02-04 & 1 & Update toolchain \\
\hline
2019-02-08 & 5 & Investigate LiteEth ethernet core \\
2020-02-08 & 5 & Investigate LiteEth ethernet core \\
\hline
2019-02-09 & 5 & Develop missing LiteEth features \\
2020-02-09 & 5 & Develop missing LiteEth features \\
\hline
2019-02-11 & 4 & Add LiteEth to SoC \\
2020-02-11 & 4 & Add LiteEth to SoC \\
\hline
2019-02-16 & 2 & LiteEth debugging firmware routines \\
2020-02-16 & 2 & LiteEth debugging firmware routines \\
\hline
2019-02-18 & 4 & LiteEth simulation model \\
2020-02-18 & 4 & LiteEth simulation model \\
\hline
2019-03-01 & 2 & Dependency updates \\
2020-03-01 & 2 & Dependency updates \\
\hline
2019-03-02 & 2 & Merge synthesis and simulation socs \\
2020-03-02 & 2 & Merge synthesis and simulation socs \\
\hline
2019-03-06 & 2 & External bus interface \\
2020-03-06 & 2 & External bus interface \\
\hline
2019-03-06 & 3 & Test external bus \\
2020-03-06 & 3 & Test external bus \\
\hline
2019-03-09 & 3 & Debug UART boot \\
2020-03-09 & 3 & Debug UART boot \\
\hline
2019-03-15 & 1 & Remove Vivado support \\
2020-03-15 & 1 & Remove Vivado support \\
\hline
2019-03-28 & 4 & Documentation \\
2020-03-28 & 4 & Documentation \\
\hline
2019-03-28 & 1 & Refactor ALU \\
2020-03-28 & 1 & Refactor ALU \\
\hline
2019-03-29 & 2 & Documentation \\
2020-03-29 & 2 & Documentation \\
\hline
2019-03-29 & 3 & Add formal verification \\
2020-03-29 & 3 & Add formal verification \\
\hline
2019-03-30 & 3 & Documentation \\
2020-03-30 & 3 & Documentation \\
\hline
2019-03-31 & 4 & Documentation \\
2020-03-31 & 4 & Documentation \\
\hline
\hline
2020-04-01 & \textbf{SUM} & 277h\\
2020-04-01 & \textbf{SUM during school year} & 150h\\
\caption{Work time reference - Brauns}
\label{tab:brauns_work}
\end{longtable}