54 lines
1.4 KiB
VHDL
54 lines
1.4 KiB
VHDL
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entity control is
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generic (
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RESET_VECTOR : yarm_word
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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fetch_enable : out std_logic;
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fetch_ready : in std_logic;
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fetch_instr_out : in yarm_word;
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decoder_enable : out std_logic;
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decoder_instr_info_out : in instruction_info_t;
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registers_data_a : in yarm_word;
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registers_data_b : in yarm_word;
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alu_enable_math : out std_logic;
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alu_math_result : in yarm_word;
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alu_valid : in std_logic;
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alu_enable_cmp : out std_logic;
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alu_cmp_result : in compare_result_t;
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csr_enable : out std_logic;
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csr_ready : in std_logic;
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csr_data_read : in yarm_word;
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csr_increase_instret : out std_logic;
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datamem_enable : out std_logic;
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datamem_ready : in std_logic;
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alignment_raise_exc : out std_logic;
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alignment_exc_data : out exception_data_t;
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registers_read_enable : out std_logic;
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registers_write_enable : out std_logic;
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-- TRAP CONTROL
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may_interrupt : out std_logic;
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-- the stage that will receive an interrupt exception
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interrupted_stage : out pipeline_stage_t;
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do_trap : in std_logic;
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trap_vector : in yarm_word;
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trap_return_vec : in yarm_word;
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return_trap : out std_logic;
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-- instruction info records used as input for the respective stages
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stage_inputs : out pipeline_frames_t
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);
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end control;
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