23 lines
584 B
VHDL
23 lines
584 B
VHDL
|
entity core is
|
||
|
|
generic (
|
||
|
|
HART_ID : natural;
|
||
|
|
RESET_VECTOR : yarm_word := (others => '0')
|
||
|
|
);
|
||
|
|
port (
|
||
|
|
clk : in std_logic;
|
||
|
|
reset : in std_logic;
|
||
|
|
|
||
|
|
-- little-endian memory interface, 4 byte address alignment
|
||
|
|
MEM_addr : out yarm_word;
|
||
|
|
MEM_read : out std_logic;
|
||
|
|
MEM_write : out std_logic;
|
||
|
|
MEM_ready : in std_logic;
|
||
|
|
MEM_byte_enable : out std_logic_vector(3 downto 0);
|
||
|
|
MEM_data_read : in yarm_word;
|
||
|
|
MEM_data_write : out yarm_word;
|
||
|
|
|
||
|
|
external_int : in std_logic;
|
||
|
|
timer_int : in std_logic;
|
||
|
|
software_int : in std_logic
|
||
|
|
);
|
||
|
|
end core;
|