entity control is
	generic (
		RESET_VECTOR : yarm_word
	);
	port (
		clk   : in std_logic;
		reset : in std_logic;

		fetch_enable    : out std_logic;
		fetch_ready     : in std_logic;
		fetch_instr_out : in yarm_word;

		decoder_enable         : out std_logic;
		decoder_instr_info_out : in instruction_info_t;

		registers_data_a : in yarm_word;
		registers_data_b : in yarm_word;

		alu_enable_math : out std_logic;
		alu_math_result : in yarm_word;
		alu_valid       : in std_logic;
		alu_enable_cmp  : out std_logic;
		alu_cmp_result  : in compare_result_t;

		csr_enable           : out std_logic;
		csr_ready            : in std_logic;
		csr_data_read        : in yarm_word;
		csr_increase_instret : out std_logic;

		datamem_enable         : out std_logic;
		datamem_ready          : in std_logic;

		alignment_raise_exc : out std_logic;
		alignment_exc_data  : out exception_data_t;

		registers_read_enable  : out std_logic;
		registers_write_enable : out std_logic;

		-- TRAP CONTROL

		may_interrupt     : out std_logic;
		-- the stage that will receive an interrupt exception
		interrupted_stage : out pipeline_stage_t;

		do_trap     : in std_logic;
		trap_vector : in yarm_word;

		trap_return_vec : in yarm_word;
		return_trap     : out std_logic;

		-- instruction info records used as input for the respective stages
		stage_inputs : out pipeline_frames_t
	);
end control;